The inventive concept relates generally to backbone channel management. More particularly, certain embodiments of the inventive concept relate to a backbone channel management method and a backbone channel management apparatus based on Advanced eXtensible Interface (AXI) protocol.
A system on chip (SoC) typically comprises a plurality of intellectual properties (IPs) that communicate with each other through various interconnections. In a typically SoC, efficient implementation of the interconnections can contribute to better system performance.
In some SoCs, IPs are connected to each other through a bus architecture, and in others, they are connected through a network on chip (NoC) topology. The NoC topology is a general network topology, and it can generally support a high density, high data flow SoC. In addition, it may allow an SoC to function at relatively high speed and with relatively low power consumption.
An SoC comprising master IPs and slave IPs may operate based on the AXI protocol. Such an SoC may use a backbone bus having a wide bit width (e.g., more than 128 bits) to reduce wire congestion and simplify implementation. However, a backbone bus having a wide bit width may reduce channel utilization while transmitting packets having different bit widths, which can decrease performance and power efficiency. It may also increase read latency and decrease the efficiency of memory scheduling.